Tuning I/O resources

Positioning the buffer cache in memory

Peripheral controllers that support 32-bit addressing are capable of DMA transfers into memory above 16MB. In this case, the size of the buffer cache is its only important feature. You can tell whether SCSI host adapters support 32-bit addressing, among other performance-enhancing features, by examining the initialization message that their device driver outputs on the system console when the system starts and the kernel is loaded. For example, the following message:

   %adapter  0x8000-0x8CDC 11       -       type=eiad ha=0 id=7 fts=std
shows that an Adaptec AHA-174x SCSI host adapter is installed which supports 32-bit DMA addresses (fts=..d). See ``Boot time messages from host adapter drivers'' for more information.

The distribution of the buffers also becomes important for controllers that only support 24-bit addressing -- these can only access the first 16MB of memory. The PLOWBUFS tunable parameter specifies the percentage of the cache buffers that the system will try to place below the 16MB boundary at boot time. During system startup, the distribution of buffers between memory above and below 16MB is displayed:

   kernel: Hz = 100, i/o bufs = 32768k (high bufs = 25232k)
To enable transfers of data between peripherals and memory above 16MB, the system makes use of multiphysical buffers situated in the lowest 16MB of memory. The amount of memory allocated for these buffers is controlled by the value of the kernel parameter NMPBUF. On systems with 24-bit controllers, you should ensure that as much of the buffer cache as possible lies in the first 16MB of memory. For more information see ``How multiphysical buffers are used''.

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© 2003 Caldera International, Inc. All rights reserved.
SCO OpenServer Release 5.0.7 -- 11 February 2003